Author Type

Graduate Student

Date of Award

1986

Document Type

Thesis

Publication Status

Version of Record

Submission Date

October 2026

Thesis/Dissertation Advisor [Chair]

Shankar, Ravi

Abstract

The concept of a Reduced Instruction Set Computer (RISC) has evolved out of a desire to enhance the performance of a computer. We present here a detailed design of a Testable Reduced Instruction Set Computer (TRISC) that utilizes a Multiple Register Set. Level Sensitive Scan Design (LSSD) is used to incorporate testability into our design. We first evolved a functional description of the design using Digital Design Language (DDL) a hardware programming language. We then entered the schematic of the design into Daisy's Logician V, a CAD/CAE workstation, using NCR CMOSII Digital Standard Cell Library. We then performed a unit delay simulation on the hierarchical design database to ascertain the logical functioning of the system.

Extent

195 p.

Comments

Source: Masters Abstracts International, Volume: 24-03, page: 0291.|College of Engineering and Computer Science|FAU Electronic Theses and Dissertations Collection|Source: Masters Abstracts International, Volume: 24-03, page: 0291.

Identifier

FADT14284

Format

pdf

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