Author Type

Graduate Student

Date of Award

2000

Document Type

Thesis

Publication Status

Version of Record

Submission Date

October 2026

Thesis/Dissertation Advisor [Chair]

Wang, Yuke

Abstract

We propose two approaches to design 1-bit full adders which can yield good performance at low power consumption. In the first approach, we design XOR/XNOR gates using a minimal number of CMOS transistors. Comparing with 10 different XOR/XNOR gates reported in literature, the new XOR/XNOR gates consume less power. The gates consisting of the smallest number of transistors are combined to create 1-bit full adders. The process is systematic and yields a total of 42 10-transistor full adders, 41 of which are new. Simulation results show that most of the new adders perform better than a previously existing 10-transistor adder and a complementary CMOS adder in terms of power and speed with heavier load. Three adders consistently perform better. In the second approach, we utilized a method called the centralized design to create four new 10-transistor full adders. Simulation results show that these new adders perform better than the previously existing 10-transistor and the complementary CMOS adder.

Extent

54 p.

Comments

College of Engineering and Computer Science|FAU Electronic Theses and Dissertations Collection|Thesis (M.S.)--Florida Atlantic University, 2000.|College of Engineering and Computer Science

Identifier

FADT15759

Format

pdf

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