Date of Award
2000
Document Type
Thesis
Publication Status
Version of Record
Submission Date
October 2026
Thesis/Dissertation Advisor [Chair]
Shankar, Ravi
Abstract
We explored the portability of various OS concepts to silicon. We wish to develop intellectual property blocks of various OS concepts, so that an embedded system designer has the option to mix and match. As a first step we have looked at inter-process communication (IPC) and Process Scheduling. We have implemented simple hardware building blocks for these. In our problem we utilize two processors, one each assigned as Master and Slave. Master is in control and implements the OS algorithms, while the Slave executes the user/application code. We show that these OS building blocks can be implemented in the hardware. Future effort of our group is to build a portfolio of OS IP blocks and explore optimization for various applications.
Extent
141 p.
Recommended Citation
Mandadi, Sanjay Reddy, "design and implementation of a simple master/slave interprocess-communication module" (2000). Electronic Theses and Dissertations 2000 - 2009. 28.
https://digitalcommons.fau.edu/etd_general_5/28
Identifier
FADT12690
Comments
College of Engineering and Computer Science|FAU Electronic Theses and Dissertations Collection|Thesis (M.S.)--Florida Atlantic University, 2000.|College of Engineering and Computer Science