Author Type

Graduate Student

Date of Award

1996

Document Type

Thesis

Publication Status

Version of Record

Submission Date

October 2026

Thesis/Dissertation Advisor [Chair]

Shankar, Ravi

Abstract

Software simulations of a scaleable VLSI implementable architecture and algorithm for character recognition by a research group at Florida Atlantic University (FAU) have shown encouraging results. We address here hardware implementation issues pertinent to the classification phase of character recognition. Using the digit classification techniques developed at FAU as a foundation, we have designed and simulated general purpose building blocks useful for a possible implementation of a Digital & Analog CMOS VLSI chip that is suitable for a variety of artificial neural network (ANN) architectures. HSPICE was used to perform circuit-level simulations of the building blocks. We present here the details of implementation of the recognition chip including the architecture, circuit design and the simulation results.

Extent

151 p.

Comments

College of Engineering and Computer Science|FAU Electronic Theses and Dissertations Collection|Thesis (M.S.)--Florida Atlantic University, 1996.|College of Engineering and Computer Science

Identifier

FADT15328

Format

pdf

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