Author Type

Graduate Student

Date of Award

1995

Document Type

Thesis

Publication Status

Version of Record

Submission Date

October 2026

Thesis/Dissertation Advisor [Chair]

Sudhakar, Raghavan

Abstract

In many scientific and signal processing applications, there are increasing demands for large volume and high speed computations, which call for not only high-speed low power computing hardware, but also for novel approaches in developing new algorithms and architectures. This thesis is concerned with the development of such architectures and algorithms suitable for the VLSI implementation of recursive and nonrecursive 1-dimension digital filters using multiple slower processing elements. As the background for the development, vectorization techniques such as state-space modeling, block processing, and look ahead computation are introduced. Concurrent architectures such as systolic arrays, wavefront arrays and appropriate parallel filter realizations such as lattice, all-pass, and wave filters are reviewed. A fully hardware efficient systolic array architecture termed as Multiplexed Block-State Filter is proposed for the high speed implementation of lattice and direct realizations of digital filters. The thesis also proposes a new simplified algorithm, Alternate Pole Pairing Algorithm, for realizing an odd order recursive filter as the sum of two all-pass filters. Performance of the proposed schemes are verified through numerical examples and simulation results.

Extent

127 p.

Comments

Graduate College|FAU Electronic Theses and Dissertations Collection|Thesis (M.S.E.)--Florida Atlantic University, 1995.|Graduate College

Identifier

FADT15155

Format

pdf

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