Author Type

Graduate Student

Date of Award

1992

Document Type

Thesis

Publication Status

Version of Record

Submission Date

October 2026

Thesis/Dissertation Advisor [Chair]

Barrett, Raymond L. Jr.

Abstract

Implementation of CMOS combinational logic with Differential Cascode Voltage Switch logic (DCVS) may have many advantages over the traditional CMOS logic approaches with respect to device count, layout density and timing. DCVS is an ideal target technology for a logic synthesis system in that it provides a complete function cover by providing the function and its complement simultaneously. DCVS is also more testable due to this. We have developed for IBM's DCVS technology a synthesis algorithm and a new test generation approach, that are based on topologies rather than individual logic functions. We have found that 19 and 363 DCVS topologies can represent 256 and 65,536 functions, respectively, for the 3- and 4-varaible cases. Physical defect analysis was conducted with the aid of a building block approach to analyze the n-type logic tree and provides a basis for evolving hierarchical test pattern generation for the topologies.

Extent

117 p.

Comments

College of Engineering and Computer Science|FAU Electronic Theses and Dissertations Collection|Thesis (M.S.C.E.)--Florida Atlantic University, 1992.|College of Engineering and Computer Science

Identifier

FADT14850

Format

pdf

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