Author Type

Graduate Student

Date of Award

1997

Document Type

Thesis

Publication Status

Version of Record

Submission Date

October 2026

Thesis/Dissertation Advisor [Chair]

Sudhakar, Raghavan

Abstract

The design of mobile communication receiver requires addressing the stringent issues of low signal-to-noise ratio (SNR) operation and low battery power consumption. Typically, forward error correction using convolutional coding with Viterbi decoding is employed to improve the error performance. However, even with moderate code lengths, the computation and storage requirement of conventional VD are substantial consuming appreciable fraction of DSP computations and hence battery power. The new error selective Viterbi decoding (ESVD) scheme developed recently (1) reduces the computational load substantially by taking advantage of the noise-free intervals to limit the trellis search. This thesis is concerned with the development of an efficient hardware architecture to implement a hard decision version of ESVD scheme for IS-54 coder. The implementations are optimized to reduce the computational complexity. The performance of the implemented ESVD scheme is verified for different channel conditions.

Extent

139 p.

Comments

College of Engineering and Computer Science|FAU Electronic Theses and Dissertations Collection|Thesis (M.S.)--Florida Atlantic University, 1997.|College of Engineering and Computer Science

Identifier

FADT15429

Format

pdf

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