Author Type

Graduate Student

Date of Award

1997

Document Type

Thesis

Publication Status

Version of Record

Submission Date

October 2026

Thesis/Dissertation Advisor [Chair]

Mahgoub, Imad

Abstract

The use of cache memories in multiprocessor systems increases the overall systems performance. Caches reduce the amount of network traffic and provide a solution to the memory contention problem. However, caches introduce memory consistency problems. The existence of multiple cache copies of a memory block will result in an inconsistent view of memory if one processor changes a value in its associated cache. Cache coherence protocols are algorithms designed in software or hardware to maintain memory consistency. With the increased complexity of some of the more recent protocols, testing for the correctness of these protocols becomes an issue that requires more elaborate work. In this thesis, correctness analysis of a selected group of representative cache coherence protocols was performed using Petri nets as a modeling and analysis tool. First, the Petri net graphs for these protocols were designed. These graphs were built by following the logical and coherence actions performed by the protocols in response to the different processors' requests that threatens memory consistency. Correctness analysis was then performed on these graphs.

Extent

119 p.

Comments

College of Engineering and Computer Science|FAU Electronic Theses and Dissertations Collection|Thesis (M.S.)--Florida Atlantic University, 1997.|College of Engineering and Computer Science

Identifier

FADT15366

Format

pdf

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