Author Type

Graduate Student

Date of Award

1987

Document Type

Thesis

Publication Status

Version of Record

Submission Date

October 2026

Thesis/Dissertation Advisor [Chair]

Shankar, Ravi

Abstract

A PCM MF Receiver based on either analog or digital filters results in a fairly large chip. A recent publication attempts to address this issue by using certain approximations that replace multiplications with simple additions and subtractions. This results in a significantly smaller chip. In our research, we have further refined/changed the algorithms and approximations in order to reduce the chip size further and the chip count to one. A simulation model corresponding to this, written in ISPS and Fortran, was extensively utilized to verify that the proposed receiver would meet and/or exceed all the commercial specifications. Subsequent to that, we initiated hardware design using structured methodologies. Hardware modules written in a high-level hardware description language have been simulated for functional validity. We expect to utilize mixed mode simulations and hierarchical design concepts in translating this high-level description to a hardware implementation on a semi-custom CMOS chip.

Extent

146 p.

Comments

College of Engineering and Computer Science|Thesis (M.S.E.)--Florida Atlantic University, 1987.|FAU Electronic Theses and Dissertations Collection|College of Engineering and Computer Science

Identifier

FADT14354

Format

pdf

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